Table of Contents

1 Formal Methods and Verification.- 1.1 Achievements in Hardware Verification.- 1.2 The HOL System.- 2 LispKit and the SECD Architecture.- 2.1 The Syntax of LispKit.- 2.2 The Interpretation of LispKit.- 2.3 SECD Architecture.- 2.4 LispKit to SECD Machine Code.- 2.5 Summary.- 3 SECD Architecture: Silicon Synthesis.- 3.1 Project Context.- 3.2 Levels of the Design.- 3.3 The Chip Interface.- 3.4 Internal Architecture and Microcode.- 3.5 The Final Layout.- 3.6 Summary and Status.- 4 Formal Specification of the SECD Design.- 4.1 Modelling Hardware.- 4.2 The Top Level Specification.- 4.3 The Low Level Definition.- 4.4 Register Transfer Level Specification.- 4.5 Relating the Levels.- 4.6 Summary.- 5 Verification of the SECD Design.- 5.1 Constraints.- 5.2 Structure of the Proof.- 5.3 Unfolding the System Definition.- 5.4 Phase Stage: Effect of Each Microinstruction.- 5.5 Microprogramming Stage: Symbolic Execution.- 5.6 Liveness.- 5.7 Computations across abstraction.- 5.8 Summary.- 6 Denouement.- 6.1 Putting the Proof Result into Context.- 6.2 Retrospective Improvements.- 6.3 Hardware Verification.

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