Table of Contents

1. Layout Design Rules: Definition, Setting and Scaling 2. Front-End-Of-Line Topological Design Rules 3. Back-End-Of-Line Topological Design Rules 4. Coverage Rules and Insertion Utilities 5. Design Rules, Guidelines and Modeling for Analog Modules 6. Stress-Related Design Rules and Modeling 7. Dedicated Design Rules for Memory Modules 8. Planar CMOS Process Flow for Digital, Mixed-Signal and RFCMOS Applications 9. Reliability Driven Design Rules

About the Author

Eitan N. Shauly is the director of integration at Tower Semiconductor Ltd., Israel, since 1998. He has been with the organization since 1989, initially as a diffusion and ion implantation engineer and a device/integration engineer and later focusing on process integration, modeling, and design rules as well as incorporating new technology in the company’s foundries. Dr Shauly also teaches courses related to VLSI technology in the Faculty of Materials Science and Engineering, Technion – Israel Institute of Technology, Haifa, Israel. He received his BSc (1989) in materials engineering from Ben-Gurion University, Beer-Sheva, Israel, and MSc (1995) and PhD (2001) in materials engineering from the Technion – Israel Institute of Technology.